The present invention relates generally to a serial data transfer circuit provided in a semiconductor integrated circuit (IC) device, and this invention is particularly suitable for a product in which a plurality of serial data transfer circuits are provided.
In the field of semiconductor IC devices, there is known a serial data transfer circuit for transferring data in units of a bit as means for communication with other devices. This serial data transfer circuit includes a register unit, a transmission unit, a reception unit and a serial clock generator.
In general, these components are integrated in the serial data transfer circuit, and serial clock signals necessary for data transfer control are generated in the serial clock generator and supplied to the transmission unit and reception unit. In the case of a product containing a plurality of such serial data transfer circuits, the generation of serial clock signals is performed individually.
FIG. 1 is a block diagram showing a conventional serial data transfer circuit. In FIG. 1, reference numeral 11 denotes a serial data transfer circuit, 12-1, 12-2 and 12-3 register units, 13 a transmission unit of the serial transfer circuit, 14 a reception unit of the serial transfer circuit, and 15 a serial clock generator.
A reference clock signal is input to the serial clock generator 15. Serial clock signals for transfer control are generated on the basis of the reference clock signal and are supplied to the transmission unit 13 and reception unit 14. Data transferred to the reception unit 14 is input to the register unit 12-3 in synchronism with the serial clock signal and is supplied to a CPU via a bus. Transfer data delivered to the register unit 12-2 via the bus from the CPU is output from the transmission unit 13 in synchronism with the serial clock signal.
The register units 12-1, 12-2 and 12-3 latch control data delivered from the CPU via the bus. Based on the latched control data, the generation of clock signals by the serial clock generator 15 and the data transfer by the transmission unit 13 and reception unit 14 are controlled.
FIG. 2 shows another conventional serial data transfer circuit. This circuit includes a serial clock generator 15-1 for the transmission unit 13 and a serial clock generator 15-2 for the reception unit 14. The transmission unit 13 and reception unit 14 perform data transfer control at different clock rates. The other structural features and operations are the same as those in FIG. 1.
In the conventional serial data transfer circuit, serial clock signals for data transfer control are generated individually in the respective serial data transfer circuits and can be used only in these respective circuits.
Thus, in the case of the product wherein a plurality of serial data transfer circuits are provided, even if the clock rate for data transfer is the same, it is necessary to set the serial data transfer circuits respectively and generate serial clock signals for data transfer control.
Moreover, even in the case where the same clock rate is achieved, the serial clock generators are operated individually. As a result, power is consumed uselessly, and a reduction in power consumption cannot be achieved.
Furthermore, since serial clock signals for transfer control cannot be shared by the two or more serial data transfer circuits. Consequently, it is not easily achieved to synchronize the serial clock signals among the two or more circuits at the time of transmission/reception.
As has been described above, in the device having the conventional serial data transfer circuits, it is necessary to individually set the serial data transfer circuits and generate serial clock signals for transfer control. Thus, the setting of the circuits is time-consuming.
Besides, in the device having the conventional serial data transfer circuits, the serial clock generators are individually operated even if the same clock rate is achieved, and a useless power consumption increases.
Furthermore, since the serial clock signals for transfer control cannot be shared by the two or more serial data transfer circuits, it is not easily achieved to synchronize the serial clock signals among the two or more circuits at the time of transmission/reception.